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| Product Overview Address Spaces Addressing Modes Memory Map SAM47 Instruction Set S3C7574/P7574 (Preliminary Spec) PRODUCT OVERVIEW 1 OVERVIEW PRODUCT OVERVIEW The S3C7574 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With features such as, DTMF Generator, LCD direct drive capability, 8-bit timer/counter, and watch timer, the S3C7574 offers an excellent design solution for a wide variety of telecommunication applications that require LCD functions. Up to 15 pins of the 64-pin QFP package, it can be dedicated to I/O. Four vectored interrupts provide fast response to internal and external events. In addition, the S3C7574's advanced CMOS technology provides for low power consumption and a wide operating voltage range. OTP The S3C7574 microcontroller is also available in OTP (One Time Programmable) version, S3P7574. The S3P7574 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM. The S3P7574 is comparable to S3C7574, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C7574/P7574 (Preliminary Spec) FEATURES Memory -- 256 x 4-bit data RAM -- 32 x 4-bit display RAM -- 4096 x 8-bit ROM I/O Pins -- Input only: 4 pins -- I/O: 11 pins -- Output: 8 pins sharing with segment driver outputs LCD Controller/Driver -- Maximum 16-digit LCD direct drive capability -- 32 segment, 4 common pins -- Display modes: Static, 1/2 duty (1/2 bias) 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) 8-Bit Basic Timer -- Programmable interval timer -- Watchdog timer 8-Bit Timer/Counter -- Programmable 8-bit timer -- External event counter -- Arbitrary clock frequency output Watch Timer -- Real-time and interval time measurement -- Four frequency outputs to BUZ pin -- Clock source generation for LCD Bit Sequential Carrier -- Support 16-bit serial data transfer in arbitrary format Operating Temperature -- - 40 C to 85 C Operating Voltage Range -- 2.0 V to 5.5 V at 4.19 MHz -- 1.8 V to 5.5 V at 3 MHz Package Type -- 64-QFP-1420F -- 64-QFP-1414 Instruction Execution Times -- 0.95, 1.91, 15.3 s at 4.19 MHz (main) -- 122 s at 32.768 kHz (subsystem) Two Power-Down Modes -- Idle mode (only CPU clock stops) -- Stop mode (main or sub system oscillation stops) Oscillation Sources -- Crystal, ceramic, or RC for main system clock -- Crystal or external oscillator for subsystem clock -- Main system clock frequency: 4.19 MHz (typical) -- Subsystem clock frequency: 32.768 kHz -- CPU clock divider circuit (by 4, 8, or 64) DTMF Generator -- 16 Dual-tone frequencies for tone dialing applications (only 3.58 MHz) Interrupts -- Two internal vectored interrupts -- Two external vectored interrupts -- Two quasi-interrupts Memory-Mapped I/O Structure -- Data memory bank 15 1-2 S3C7574/P7574 (Preliminary Spec) PRODUCT OVERVIEW BLOCK DIAGRAM RESET INT0, INT1, INT2 XIN XOUT XTIN XTOUT Basic Timer Watch Timer P2.3/BUZ P1.3/TCL0 P2.0/TCLO0 8-Bit Timer Counter 0 Interrupt Control Block Clock Instruction Register LCD Driver/ Controller BIAS VLC0-VLC2 LCDCK/P3.0 LCDSY/P3.1 SEG0-SEG23 COM0-COM3 SEG24-SEG31 /P8.0-P8.7 P6.0-P6.3/ KS0-KS3 Internal Interrupts I/O Port 6 Instruction Decoder Program Counter Input Port 1 Program Status Word P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/TCL0 P2.0/TCLO0 P2.1 P2.2/CLO P2.3/BUZ P3.0/LCDCK P3.1/LCDSY P3.2 P8.0-P8.7/ SEG24-SEG31 Output Port 8 Arithmetic and Logic Unit I/O Port 2 Stack Pointer I/O Port 3 288 x 4-Bit Data Memory 4-Kbyte Program Memory DTMF Generator DTMF Figure 1-1. S3C7574 Simplified Block Diagram 1-3 PRODUCT OVERVIEW S3C7574/P7574 (Preliminary Spec) PIN ASSIGNMENTS 64 63 62 61 60 59 58 57 56 55 54 53 52 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 COM0 COM1 COM2 COM3 BIAS VLC0 VLC1 VLC2 VDD VSS XOUT XIN TEST XTIN XTOUT RESET P1.0/INT0 P1.1/INT1 P1.2/INT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 S3C7574 (64-QFP) 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24/P8.0 SEG25/P8.1 SEG26/P8.2 SEG27/P8.3 SEG28/P8.4 SEG29/P8.5 SEG30/P8.6 SEG31/P8.7 Figure 1-2. S3C7574 64-QFP Pin Assignment 1-4 P1.3/TCL0 P2.0/TCLO0 P2.1 P2.2/CLO P2.3/BUZ P3.0/LCDCK P3.1/LCDSY P3.2 DTMF P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 20 21 22 23 24 25 26 27 28 29 30 31 32 S3C7574/P7574 (Preliminary Spec) PRODUCT OVERVIEW 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM0 COM1 COM2 COM3 BIAS VLC0 VLC1 VLC2 VDD VSS XOUT XIN TEST XTIN XTOUT RESET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S3C7574 (64-QFP) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24/P8.0 SEG25/P8.1 SEG26/P8.2 SEG27/P8.3 SEG28/P8.4 SEG29/P8.5 SEG30/P8.6 SEG31/P8.7 Figure 1-3. S3C7574 64-QFP Pin Assignment P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/TCL0 P2.0/TCLO0 P2.1 P2.2/CLO P2.3/BUZ P3.0/LCDCK P3.1/LCDSY P3.2 DTMF P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1-5 PRODUCT OVERVIEW S3C7574/P7574 (Preliminary Spec) PIN DESCRIPTIONS Table 1-1. S3C7574 Pin Descriptions Pin Name P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 Pin Type I Description 4-bit input port. 1-bit or 4-bit read and test is possible. 4-bit pull-up resistors are software assignable. 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable. 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. Each individual pin can be specified as input or output. 4-bit pull-up resistors are software assignable. 4-bit I/O ports. Pins are individually software configurable as input or output. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable. Output port for 1-bit data (for use as CMOS driver only) DTMF output LCD segment signal output LCD segment signal output LCD common signal output LCD power supply. Built-in voltage dividing resistors LCD power control LCD clock output for display expansion Number 17 18 19 20 21 22 23 24 25 26 27 Share Pin INT0 INT1 INT2 TCL0 TCLO0 - CLO BUZ LCDCK LCDSY - Reset Value Input Circuit Type A-4 I/O Input D I/O Input D P6.0-P6.3 I/O 29-32 KS0-KS3 Input D P8.0-P8.7 DTMF SEG0-SEG23 SEG24-SEG31 COM0-COM3 VLC0-VLC2 BIAS LCDCK O O O O O - - I/O 33-40 28 41-64 33-40 1-4 6-8 5 25 SEG24- SEG31 - P8.0-P8.7 - - - P3.0 Output Output Output Output Output - - Input H-1 G-6 H H-1 H - - D 1-6 S3C7574/P7574 (Preliminary Spec) PRODUCT OVERVIEW Table 1-1. S3P7574 Pin Descriptions (Continued) Pin Name LCDSY TCL0 TCLO0 INT0 INT1 Pin Type I/O I I/O I Description LCD synchronization clock output for LCD display expansion External clock input for timer/counter 0 Timer/counter 0 clock output External interrupt. The triggering edge for INT0 and INT1 is selectable. Only INT0 is synchronized with the system clock. Quasi-interrupt with detection of rising edge signals. Quasi-interrupt input with falling edge detection. CPU clock output 2, 4, 8 or 16 kHz frequency output for buzzer sound with 4.19 MHz main system clock or 32.768 kHz subsystem clock. Crystal, ceramic or RC oscillator pins for main system clock. (For external clock input, use XIN and input XIN's reverse phase to XOUT) Crystal oscillator pins for subsystem clock. (For external clock input, use XTIN and input XTIN's reverse phase to XTOUT) Main power supply Ground Reset signal Test signal input (must be connected to VSS) Number 26 20 21 17 18 Share Pin P3.1 P1.3 P2.0 P1.0 P1.1 Reset Value Input Input Input Input Circuit Type D A-4 D A-4 INT2 KS0-KS3 CLO BUZ I I/O I/O I/O 19 29-32 23 24 P1.2 P6.0-P6.3 P2.2 P2.3 Input Input Input Input A-4 D D D XIN, XOUT - 11, 12 - - - XTIN, XTOUT - 14, 15 - - - VDD VSS RESET - - - - 9 10 16 13 - - - - - - Input - - - B - TEST NOTE: Pull-up resistors for all I/O ports automatically disabled if they are configured to output mode. 1-7 PRODUCT OVERVIEW S3C7574/P7574 (Preliminary Spec) PIN CIRCUIT VDD VDD P-Channel Data In N-Channel Output Disable P-CH Out N-CH Figure 1-4. Pin Circuit Type A Figure 1-6. Pin Circuit Type C VDD VDD Pull-up Resistor Resistor Enable In Resistor Enable Data Output Disable Pull-up Resistor P-Channel Circuit Type C I/O Schmitt Trigger Circuit Type A Figure 1-5. Pin Circuit Type A-4 (P1) Figure 1-7. Pin Circuit Type D (P2, P3, and P6) 1-8 S3C7574/P7574 (Preliminary Spec) PRODUCT OVERVIEW VLC0 VLC1 VDD LCD Segment/ Common Data Out In Schmitt Trigger VLC2 Figure 1-8. Pin Circuit Type H (SEG/COM) Figure 1-10. Pin Circuit Type B (RESET) VDD VLC0 VLC1 LCD Segment/ & Port 8 Data Out Disable VLC2 DTMF Out + Figure 1-9. Pin Circuit Type H-1 (P8) Figure 1-11. Pin Circuit Type G-6 (DTMF) 1-9 S3C7574/P7574 (Preliminary Spec) ELECTRICAL DATA 14 OVERVIEW -- I/O capacitance ELECTRICAL DATA In this section, information on S3C7574 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics -- Absolute maximum ratings -- D.C. electrical characteristics -- Main system clock oscillator characteristics -- Subsystem clock oscillator characteristics -- A.C. electrical characteristics -- Operating voltage range Miscellaneous Timing Waveforms -- A.C timing measurement point -- Clock timing measurement at XIN -- Clock timing measurement at XTIN -- TCL0 timing -- Input timing for RESET -- Input timing for external interrupts Stop Mode Characteristics and Timing Waveforms -- RAM data retention supply voltage in stop mode -- Stop mode release timing when initiated by RESET -- Stop mode release timing when initiated by an interrupt request 14-1 ELECTRICAL DATA S3C7574/P7574 (Preliminary Spec) Table 14-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI1 VO I OH I OL One I/O port active All I/O ports active Output Current Low One I/O port active All I/O ports Conditions - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 30 + 30 (Peak value) + 15 (note) Total value for ports 2 and 3 Total value for port 6 Operating Temperature Storage Temperature TA Tstg - - + 60 (Peak value) + 20 + 50 + 20 (note) (note) Units V mA - 40 to + 85 - 65 to + 150 Duty . C NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value x Table 14-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input high voltage Symbol VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 VIL3 Output high voltage VOH1 Conditions All input pins except those specified below for VIH2, VIH3 Ports 1, 6, and RESET XIN, XOUT, and XTIN Ports 2 and 3 Ports 1, 6 and RESET XIN, XOUT, and XTIN VDD = 4.5 V to 5.5 V IOH = - 1 mA Ports 2, 3, 6 and BIAS VDD = 4.5 V to 5.5 V IOH = -100 A Port 8 only Min 0.7 VDD 0.8 VDD VDD - 0.1 - - - VDD - 1.0 Typ - - - - - - - Max VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 - V V Units V VOH2 VDD - 2.0 - - 14-2 S3C7574/P7574 (Preliminary Spec) ELECTRICAL DATA Table 14-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Output low voltage Symbol VOL1 VOL2 Input high leakage current ILIH1 Conditions VDD = 4.5 V to 5.5 V IOL = 15 mA, Ports 2, 3, 6 VDD = 4.5 V to 5.5 V IOL = 100 A; Port 8 only VIN = VDD All input pins except those specified below for ILIH2 VIN = VDD XIN, XOUT and XTIN VIN = 0 V All input pins except XIN, XOUT, and XTIN VIN = 0 V XIN, XOUT, and XTIN VOUT = VDD All output pins VOUT = 0 V All output pins VIN = 0 V; VDD = 5 V Ports 1, 2, 3, 6 VDD = 3 V RL2 VIN = 0 V; VDD = 5 V RESET Min - - - Typ 0.4 - - Max 2 1 3 Units V A ILIH2 Input low leakage current ILIL1 20 - - -3 ILIL2 Output high leakage current Output low leakage current Pull-up resistor ILOH1 ILOL RL1 - 20 - - 3 -3 25 50 100 50 100 250 100 200 400 K A VDD = 3 V LCD voltage dividing resistor COM output impedance SEG output impedance COM output voltage deviation VDC RSEG RLCD RCOM TA = 25 C VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V (VLC0-COMi) IO = uA (I = 0-3) 200 100 - 500 150 3 5 3 5 45 800 200 6 15 6 15 90 mV - 14-3 ELECTRICAL DATA S3C7574/P7574 (Preliminary Spec) Table 14-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter SEG output voltage deviation VLC0 Output voltage VLC1 Output voltage VLC2 Output voltage Symbol VDS VLC0 VLC1 VLC2 Conditions VDD = 5 V (VLC0-EGi) IO = 15 uA (i = 031) TA = 25 C TA = 25 C TA = 25 C Min - 0.6 VDD - 0.2 0.4 VDD - 0.2 0.2 VDD - 0.2 Typ 45 0.6 VDD 0.4 VDD 0.2 VDD Max 90 0.6 VDD + 0.2 0.4 VDD + 0.2 0.2 VDD + 0.2 Units mV V 14-4 S3C7574/P7574 (Preliminary Spec) ELECTRICAL DATA Table 14-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Conditions Main operating: IDD1 VDD = 5 V 10 % (DTMF On) CPU = fx/4 SCMOD = 0000B Crystal oscillator C1 = C2 = 22 pF (2) Symbol Min 3.58 MHz - Typ 3.9 Max 7.0 Units mA VDD = 3 V 10 % Main idle mode; V = 5 V 10 % (DTMF Off) DD CPU = fx/4 SCMOD =0000B Crystal oscillator C1 = C2 = 22 pF IDD2 (2) VDD = 3 V 10 % IDD3 (2) Main operating: VDD = 5 V 10 % CPU = fx/4, SCMOD = 0000B Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10 % IDD4 Sub operating: VDD = 3 V 10 % CPU = fxt/4, SCMOD = 1001B 32 kHz crystal oscillator Sub idle mode: VDD = 3 V 10 % CPU = fxt/4, SCMOD = 1001B 32 kHz crystal oscillator Stop mode; VDD = 5 V 10 % VDD = 3 V 10 % Stop mode; VDD = 5 V 10 % VDD = 3 V 10 % SCMOD = 0000B XTIN = 0 V SCMOD = 0100B 6.0 MHz 3.58 MHz - 2.0 3.5 2.5 4.0 8.0 5.0 6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz - 1.6 1.2 1.0 0.9 4.0 2.3 2.5 1.8 6.0 MHz 3.58 MHz - 0.5 0.4 15 1.0 0.8 30 A IDD5 - 6 15 IDD6 - 2.0 0.6 0.2 0.1 5 3 3 2 14-5 ELECTRICAL DATA S3C7574/P7574 (Preliminary Spec) Table 14-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Row Tone Level Ratio of Column to Row tone Distortion (Dual tone) Symbol VROW dBCR Conditions VDD = 2.0 to 5.5 V RL = 12 k; Temp = - 30 to 60 C VDD = 2.0 to 5.5 V 1 2 3 dB RL = 12 k; Temp = - 30 to 60 C VDD = 2.0 to 5.5 V 1 MHz band RL = 12 k; Temp = - 30 to 60 C - - 5 % Min - 16.0 Typ -14.0 Max -12.0 Units dBV THD NOTES: 1. D.C. electrical values for supply current (IDD1 to IDD7) do not include current drawn through internal pull-up resistors and through LCD voltage dividing resistors. 2. Data includes the power consumption for sub-system clock oscillation. 3. When the system clock mode register, SCMOD, is set to 0100B, the sub-system clock oscillation stops. The mainsystem clock oscillation stops by the STOP instruction. 14-6 S3C7574/P7574 (Preliminary Spec) ELECTRICAL DATA Table 14-3. Main System Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration XIN XOUT (1) Parameter Oscillation frequency Test Condition - Min 0.4 Typ - Max 6.0 Units MHz C1 C2 Stabilization time (2) Stabilization occurs when VDD is equal to the minimum oscillator voltage range. - - - 4 ms Crystal Oscillator XIN XOUT Oscillation frequency (1) 0.4 - 6.0 MHz C1 C2 Stabilization time (2) VDD = 4.5 V to 5.5 V VDD = 1.8 V to 4.5 V - - 0.4 - - - 10 30 6.0 ms External Clock XIN XOUT XIN input frequency (1) - MHz XIN input high and low level width (tXH, tXL) RC Oscillator XIN R XOUT - VDD = 5 V R = 20 K, VDD = 5 V R = 39 K, VDD = 3 V 83.3 0.4 - - 2.0 1.0 - 2 ns MHz Frequency (1) NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is terminated. 14-7 ELECTRICAL DATA S3C7574/P7574 (Preliminary Spec) Table 14-4. Subsystem Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Oscillator Clock Configuration XTIN XTOUT (1) Parameter Oscillation frequency Test Condition - Min 32 Typ 32.768 Max 35 Units kHz C1 C2 Stabilization time (2) VDD = 4.5 V to 5.5 V VDD = 1.8 V to 4.5 V - - 32 1.0 - - 2 10 100 s External Clock XTIN XTOUT XTIN input frequency (1) - kHz XTIN input high and low level width (tXTL, tXTH) - 5 - 15 s NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs. 14-8 S3C7574/P7574 (Preliminary Spec) ELECTRICAL DATA Table 14-5. Input/output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - - - Typ - - - Max 15 15 15 Units pF pF pF Table 14-6. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Instruction cycle time (1) TCL0 input frequency TCL0 input high, low width Interrupt input high, low width RESET Input Low Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V With subsystem clock (fxt) Min 0.67 0.95 114 0 Typ - - 122 - Max 64 64 125 1.5 1 Units s f TI0 tTIH0, tTIL0 tINTH, tINTL tRSL VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V INT0 INT1, INT2, KS0-KS3 Input MHz MHz s s s 0.48 1.8 (2) - - - - 10 10 - - Width NOTES: 1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock (fx) source. 2. Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting. 14-9 ELECTRICAL DATA S3C7574/P7574 (Preliminary Spec) CPU Clock 1.5 MHz 1.0475 MHz 750 kHz 500 kHz 250 kHz Main Oscillator Frequency 6 MHz 4.19 MHz 3 MHz 15.6 kHz 1 2 3 4 5 6 7 Supply Voltage (V) CPU Clock = 1/n x oscillator frequency (n = 4, 8, 64) Figure 14-1. Standard Operating Voltage Range Table 14-7. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions Normal operation VDDDR = 2.0 V Normal operation Released by RESET Released by interrupt Min 1.5 - 0 - - Typ - 0.1 - 217/fx (2) Max 6.5 1 - - - Unit V A s ms NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator startup. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time. 14-10 S3C7574/P7574 (Preliminary Spec) ELECTRICAL DATA TIMING WAVEFORMS Internal RESET Operation Stop Mode Data Retention Mode Idle Mode Operating Mode ~ ~ ~ ~ VDD VDDDR Execution of STOP Instrction RESET tWAIT tSREL Figure 14-2. Stop Mode Release Timing When Initiated by RESET Idle Mode ~ ~ ~ ~ Stop Mode Data Retention Mode Normal Operating Mode VDD VDDDR Execution of STOP Instrction tSREL tWAIT Power-down Mode Terminating Signal (Interrupt Request) Figure 14-3. Stop Mode Release Timing When Initiated by Interrupt Request 14-11 ELECTRICAL DATA S3C7574/P7574 (Preliminary Spec) 0.8 VDD Measurement Points 0.2 VDD 0.8 VDD 0.2 VDD Figure 14-4. A.C. Timing Measurement Points (Except for XIN and XT IN) 1/fx tXL tXH XIN VDD - 0.1 V 0.1 V Figure 14-5. Clock Timing Measurement at XIN 1/fxt tXTL tXTH XTIN VDD - 0.1 V 0.1 V Figure 14-6. Clock Timing Measurement at XT IN 14-12 S3C7574/P7574 (Preliminary Spec) ELECTRICAL DATA 1/fTI0 tTIL0 tTIH0 TCL0 0.8 VDD 0.2 VDD Figure 14-7. TCL0 Timing tRSL RESET 0.2 VDD Figure 14-8. Input Timing for RESET Signal tINTL tINTH INT0, 1, 2, 4, KS0 to KS3 0.8 VDD 0.2 VDD Figure 14-9. Input Timing for External Interrupts and Quasi-Interrupts 14-13 S3C7574/P7574 (Preliminary Spec) MECHANICAL DATA 15 OVERVIEW MECHANICAL DATA The S3C7574 microcontroller is available in a 64-pin QFP package (Samsung: 64-QFP-1420F and 64-QFP1414). Package dimensions are shown in Figure 15-1 and Figure 15-2. 23.90 0.30 20.00 0.20 0-8 + 0.10 0.15 - 0.05 17.90 0.30 14.00 0.20 64-QFP-1420F 0.80 0.20 #1 1.00 + 0.10 0.10 MAX #64 0.40 - 0.05 0.15 MAX 0.05 MIN (1.00) 2.65 0.10 3.00 MAX 0.80 0.20 NOTE: Dimensions are in millimeters. Figure 15-1. 64-QFP-1420F Package Dimensions 15-1 MECHANICAL DATA S3C7574/P7574 (Preliminary Spec) 17.20 0.30 14.00 0.20 0-8 0.15 + 0.10 - 0.05 17.20 0.30 14.00 0.20 64-QFP-1414 0.80 0.20 #1 0.80 0.35 0.10 0.10 MAX #64 0.05 MIN (1.00) 2.60 0.10 2.80 MAX NOTE: Dimensions are in millimeters. Figure 15-2. 64-QFP-1414 Package Dimensions. 15-2 S3C7574/P7574 (Preliminary Spec) S3P7574 OTP 16 OVERVIEW S3P7574 OTP The S3P7574 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C7574 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a serial data format. The S3P7574 is fully compatible with the S3C7574, both in function and in pin configuration. Because of its simple programming requirements, the S3P7574 is ideal for use as an evaluation chip for the S3C7574. 16-1 S3P7574 OTP S3C7574/P7574 (Preliminary Spec) 64 63 62 61 60 59 58 57 56 55 54 53 52 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 COM0 COM1 COM2 COM3 BIAS VLC0 SDAT/VLC1 SCLK/VLC2 VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT RESET/RESET RESET P1.0/INT0 P1.1/INT1 P1.2/INT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 S3P7574 (64-QFP) 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24/P8.0 SEG25/P8.1 SEG26/P8.2 SEG27/P8.3 SEG28/P8.4 SEG29/P8.5 SEG30/P8.6 SEG31/P8.7 Figure 16-1. S3P7574 Pin Assignments (64-QFP) 16-2 P1.3/TCL0 P2.0/TCLO0 P2.1 P2.2/CLO P2.3/BUZ P3.0/LCDCK P3.1/LCDSY P3.2 DTMF P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 20 21 22 23 24 25 26 27 28 29 30 31 32 S3C7574/P7574 (Preliminary Spec) S3P7574 OTP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM0 COM1 COM2 COM3 BIAS VLC0 SDAT/VLC1 SCLK/VLC2 VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT RESET/RESET RESET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S3P7574 (64-QFP) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24/P8.0 SEG25/P8.1 SEG26/P8.2 SEG27/P8.3 SEG28/P8.4 SEG29/P8.5 SEG30/P8.6 SEG31/P8.7 Figure 16-2. S3P7574 Pin Assignments (64-QFP) P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/TCL0 P2.0/TCLO0 P2.1 P2.2/CLO P2.3/BUZ P3.0/LCDCK P3.1/LCDSY P3.2 DTMF P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16-3 S3P7574 OTP S3C7574/P7574 (Preliminary Spec) Table 16-1. Pin Descriptions Used to Read/Write the EPROM Main Chip Pin Name VLC1 Pin Name SDAT Pin No. 7 During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip initialization Logic power supply pin. VDD should be tied to + 5 V during programming. VLC2 TEST SCLK VPP (TEST) 8 13 I/O I RESET VDD/VSS RESET VDD/VSS 16 9/10 I I Table 16-2. Comparison of S3P7574 and S3C7574 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability S3P7574 4-Kbyte EPROM 2.0 V to 5.5 V at 4.19 MHz 1.8 V to 5.5 V at 3 MHz VDD = 5 V, VPP (TEST) = 12.5 V 64 QFP User Program 1 time 64 QFP Programmed at the factory S3C7574 4-Kbyte mask ROM 2.0 V to 5.5 V at 4.19 MHz 1.8 V to 5.5 V at 3 MHz - OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of the S3P7574, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16-3 below. Table 16-3. Operating Mode Selection Criteria VDD 5V Vpp (TEST) 5V 12.5 V 12.5 V 12.5 V REG/ MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH R/W W 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection Mode NOTE: "0" means low level; "1" means high level. 16-4 S3C7574/P7574 (Preliminary Spec) S3P7574 OTP Table 16-4. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input high voltage Symbol VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 VIL3 Output high voltage VOH1 Conditions All input pins except those specified below for VIH2, VIH3 Ports 1, 6, and RESET XIN, XOUT, and XTIN Ports 2 and 3 Ports 1, 6 and RESET XIN, XOUT, and XTIN VDD = 4.5 V to 5.5 V IOH = - 1 mA Ports 2, 3, 6 and BIAS VDD = 4.5 V to 5.5 V IOH = -100 A Port 8 only VDD = 4.5 V to 5.5 V IOL = 15 mA, Ports 2, 3, 6 VDD = 4.5 V to 5.5 V IOL = 100 A; Port 8 only VIN = VDD All input pins except those specified below for ILIH2 VIN = VDD XIN, XOUT and XTIN VIN = 0 V All input pins except XIN, XOUT, and XTIN VIN = 0 V XIN, XOUT, and XTIN VOUT = VDD All output pins VOUT = 0 V All output pins Min 0.7 VDD 0.8 VDD VDD-0.1 - - - VDD-1.0 Typ - - - - - - - Max VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 - V V Units V VOH2 Output low voltage VOL1 VOL2 Input high leakage current ILIH1 VDD-2.0 - - - - 0.4 - - - 2 1 3 A V ILIH2 Input low leakage current ILIL1 - - - - 20 -3 A ILIL2 Output high leakage current Output low leakage current ILOH1 - - - - - 20 3 A ILOL - - -3 16-5 S3P7574 OTP S3C7574/P7574 (Preliminary Spec) Table 16-4. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Pull-up resistor Symbol RL1 Conditions VIN = 0 V; VDD = 5 V Ports 1, 2, 3, 6 VDD = 3 V RL2 VIN = 0 V; VDD = 5 V RESET Min 25 50 100 Typ 50 100 250 Max 100 200 400 Units K VDD = 3 V LCD voltage dividing resistor COM output impedance SEG output impedance COM output voltage deviation SEG output voltage deviation VLC0 Output voltage VLC1 Output voltage VLC2 Output voltage VLC1 VLC2 TA = 25 C TA = 25 C VDC RSEG RLCD TA = 25 C VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V (VLC0-COMi) IO = 15 uA (I = 0-3) VDD = 5 V (VLC0-SEGi) IO = 15 uA (I = 0-31) TA = 25 C 200 100 500 150 800 200 RCOM - 3 5 3 5 6 15 6 15 90 mV - 45 VDS - 45 90 mV VLC0 0.6 VDD - 0.2 0.4 VDD - 0.2 0.2 VDD - 0.2 0.6 VDD 0.4 VDD 0.2 VDD 0.6 VDD + 0.2 0.4 VDD + 0.2 0.2 VDD + 0.2 V 16-6 S3C7574/P7574 (Preliminary Spec) S3P7574 OTP Table 16-4. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 (2) Conditions Main operating: VDD = 5 V 10 % CPU = fx/4 SCMOD = 0000B Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10 % Min 6.0 MHz 4.19 MHz - Typ 3.5 2.5 Max 8 5.5 Units mA 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz - 1.6 1.2 1 0.9 4 3 2.5 2 IDD2 (2) Main idle mode; VDD = 5 V 10% CPU = fx/4 SCMOD =0000B Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10% 6.0 MHz 4.19 MHz - 0.5 0.4 15 1.0 0.8 30 A IDD3 IDD4 Sub operating: VDD = 3 V 10 % CPU = fxt/4, SCMOD = 1001B 32 kHz crystal oscillator Sub idle mode: VDD = 3 V 10 % CPU = fxt/4, SCMOD = 1001B 32 kHz crystal oscillator Stop mode: VDD = 5 V 10 % CPU=fxt/4, SCMOD = 1101B Stop mode: VDD = 5 V 10% CPU = fx/4, SCMOD = 0100B - 6 15 IDD5 - 0.5 3 IDD6 (3) NOTES: 1. D.C. electrical values for supply current (IDD1 to IDD6) do not include current drawn through internal pull-up resistors 2. 3. and through LCD voltage dividing resistors. Data includes the power consumption for sub-system clock oscillation. When the system clock mode register, SCMOD, is set to 0100B, the sub-system clock oscillation stops. The mainsystem clock oscillation stops by the STOP instruction. 16-7 KS57P2304 OTP KS57C2302/C2304/P2304 MICROCONTROLLER CPU Clock 1.5 MHz 1.0475 MHz 750 kHz 500 kHz 250 kHz Main Oscillator Frequency 6 MHz 4.19 MHz 3 MHz 15.6 kHz 1 2 3 4 5 6 7 Supply Voltage (V) CPU Clock = 1/n x oscillator frequency (n = 4, 8, 64) Figure 16-3. Standard Operating Voltage Range IOL (mA) 35.00 VDD= 5.5 V VDD= 4.5 V 3.500/div VDD= 3.3 V VDD= 2.2 V .0000 .0000 .2000/div 2.000 VOL (V) Figure 16-4. Port 2 IOL vs VOL Curve 16-8 |
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